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Ordering number : EN*5223
CMOS LSI
LC78621E
Compact Disc Player DSP
Preliminary Overview
The LC78621E is a CMOS LSI that implements the signal processing and servo control required by compact disk players, laser disks, CD-V, CD-I and related products. The LC78621E provides several types of signal processing, including demodulation of the optical pickup EFM signal, de-interleaving, error detection and correction, and digital filters that can help reduce the cost of CD player units. It also processes a rich set of servo system commands sent from the control microprocessor. It also incorporates an EFM-PLL circuit and a one-bit D/A converter. * Support for command input from a control microprocessor: commands include track jump, focus start, disk motor start/stop, muting on/off and track count (8 bit serial input) * Built-in digital output circuits. * Arbitrary track counting to support high-speed data access * Zero cross muting * Supports the implementation of a double-speed dubbing function. * D/A converter outputs with data continuity improved by 8x oversampling digital filters. (These filters function as 4x oversampling filters during double-speed playback.) * Built-in third-order D/A converters (PWM output) * Built-in digital attenuator (8 bits - alpha, 239 steps) * Built-in digital de-emphasis * Built-in digital level and peak meter functions * Support for bilingual applications
Functions
* Input signal processing: The LC78621E takes an HF signal as input, digitizes (slices) that signal at a precise level, converts that signal to an EFM signal, and generates a PLL clock with an average frequency of 4.3218 MHz by comparing the phases of that signal and an internal VCO. * Precise reference clock and necessary internal timing generation using an external 16.9344 MHz crystal oscillator * Disk motor speed control using a frame phase difference signal generated from the playback clock and the reference clock * Frame synchronization signal detection, protection and interpolation to assure stable data readout * EFM signal demodulation and conversion to 8-bit symbol data * Subcode data separation from the EFM demodulated signal and output of that data to an external microprocessor * Subcode Q signal output to a microprocessor over the serial I/O interface after performing a CRC error check * Demodulated EFM signal buffering in internal RAM to handle up to 4 frames of disk rotational jitter * Demodulated EFM signal reordering in the prescribed order for data unscrambling and de-interleaving * Error detection, correction, and flag processing (error correction scheme: dual C1 plus dual C2 correction) * The LC78620E sets the C2 flags based on the C1 flags and a C2 check, and then performs signal interpolation or muting depending on the C2 flags. The interpolation circuit uses a quadruple interpolation scheme. The output value converges to the muting level when four or more consecutive C2 flags occur.
Features
* 80-pin QIP (miniature, reduced space package) * Silicon gate CMOS process (for low power) * 5 V single-voltage power supply (for use in portable products)
Package Dimensions
unit: mm 3174-QFP80E
[LC78621E]
SANYO: QIP80E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
83095HA (OT) No. 5223-1/34
LC78621E Equivalent Circuit Block Diagram
Pin Assignment
No. 5223-2/34
LC78621E
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN max VOUT max Pd max Topr Tstg Conditions Ratings VSS - 0.3 to VSS + 7.0 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 300 -20 to +75 -40 to +125 Unit V V V mW C C
Allowable Operating Ranges at Ta = 25C, VSS = 0 V
Parameter Supply voltage Symbol VDD VIH (1) VIH (2) VIL (1) VIL (2) Data setup time Data hold time High-level clock pulse width Low-level clock pulse width Data read access time Command transfer time Subcode Q read enable time Subcode read cycle Subcode read enable time Input level Operating frequency range Crystal oscillator frequency tset up thold tWoH tWoL tRAC tRWC tSQE tsc tse VIN (1) VIN (2) fop fX (1) fX (2) Conditions VDD, XVDD, LVDD, RVDD, VVDD DEFI, FZD, ASDACK, ASDFIN, ASDFIR, ASLRCK, COIN, RES, HFL, TES, SBCK, RWC, CQCK, TAI, TEST1 to TEST5, DEMO, CS EFMIN DEFI, FZD, ASDACK, ASDFIN, ASDFIR, ASLRCK, COIN, RES, HFL, TES, SBCK, RWC, CQCK, TAI, TEST1 to TEST5, DEMO, CS EFMIN COIN, RWC: Figure 1 COIN, RWC: Figure 1 SBCK, CQCK: Figures 1, 2 and 3 SBCK, CQCK: Figures 1, 2 and 3 SQOUT, PW: Figures 2 and 3 RWC: Figure 1 WRQ: Figure 2, with no RWC signal SFSY: Figure 3 SFSY: Figure 3 EFMIN XIN: Input capacitor coupled EFMIN XIN, XOUT: In 16M mode XIN, XOUT: In 32M mode 16.9344 33.8688 400 1.0 1.0 10 min 3.6 0.7 VDD 0.6 VDD 0 0 400 400 400 400 0 1000 11.2 136 400 typ max 5.5 VDD VDD 0.3 VDD 0.4 VDD Unit V V V V V ns ns ns ns ns ns ms s ns Vp-p Vp-p MHz MHz MHz
Input high-level voltage
Input low-level voltage
Note: Due to the structure of this LSI, an identical voltage must be supplied to all the power supply pins.
Electrical Characteristics at Ta = 25C, VDD = 5 V, VSS = 0 V
Parameter Current drain Symbol IDD IIH (1) IIH (2) Input low-level current IIL DEFI, EFMIN, FZD, ASDACK, ASDFIN, ASDFIR, ASLRCK, COIN, RES, HFL, TES, SBCK, RWC, CQCK: VIN = 5 V TAI, TEST1 to TEST5, DEMO, CS: VIN = VDD = 5.5 V DEFI, EFMIN, FZD, ASDACK, ASDFIN, ASDFIR, ASLRCK, COIN, RES, HFL, TES, SBCK, RWC, CQCK, TAI, TEST1 to TEST5, DEMO, CS: VIN = 0 V EFMO, EFMO, CLV+, CLV-, V/P, FOCS, PCK, FSEQ, TOFF, TGL, THLD, JP+, JP-, EMPH, EFLG, FSX: IOH = -1 mA MUTEL, MUTER, LRCKO, DFORO, DFOLO, DACKO, TST10, LRSY, CK2, ROMXA, C2F, SBSY, PW, SFSY, WRQ, SQOUT, TST11, 16M, 4.2M, CONT: IOH = -0.5 mA LASER: IOH = -1 mA DOUT: IOH = -12 mA LCHP, RCHP, LCHN, RCHN: IOH = -1mA 25 -5 Conditions min typ 30 max 45 5 75 Unit mA A A A
Input high-level current
VOH (1)
4
V
Output high-level voltage
VOH (2) VOH (3) VOH (4) VOH (5)
4
V
4.6 4.5 3.0 4.5
V V V
Continued on next page. No. 5223-3/34
LC78621E
Continued from preceding page. Parameter Symbol VOL (1) Conditions EFMO, EFMO, CLV+, CLV-, V/P, FOCS, PCK, FSEQ, TOFF, TGL, THLD, JP+, JP-, EMPH, EFLG, FSX: IOL = 1 mA MUTEL, MUTER, LRCKO, DFORO, DFOLO, DACKO, TST10, LRSY, CK2, ROMXA, C2F, SBSY, PW, SFSY, WRQ, SQOUT, TST11, 16M, 4.2M, CONT, LASER: IOL = 2 mA DOUT: IOL = 12 mA FST: IOL = 5 mA LCHP, RCHP, LCHN, RCHN: IOL = 1mA PDO, CLV+, CLV-, JP+, JP-, FST: VOUT = 5 V PDO, CLV+, CLV-, JP+, JP-: VOUT = 0 V PDO: RISET = 68 k PDO: RISET = 68 k -5 100 -150 125 -125 150 -100 0.5 min typ max 1 Unit V
Output low-level voltage
VOL (2) VOL (3) VOL (4) VOL (5) IOFF (1) IOFF (2) IPDOH IPDOL
0.4
V
0.5 0.75 2.0 5
V V V A A A A
Output off leakage current
Charge pump output current
Note: For guaranteed operation, the VCO oscillator frequency range adjustment resistor FR must be a 1.20 k (5.0%) tolerance resistor.
One-Bit D/A Converter Analog Characteristics at Ta = 25C, VDD = LVDD = RVDD = 5 V, VSS = LVSS = RVSS = 0 V
Parameter Total harmonic distortion Symbol THD + N Conditions LCHP, RCHP, LCHN, RCHN; 1 kHz: 0 dB data input, using the 20 kHz low-pass filter (AD725D built in) LCHP, RCHP, LCHN, RCHN; 1 kHz: -60 dB data input, using the 20 kHz low-pass filter and the A filter (AD725D built in) LCHP, RCHP, LCHN, RCHN; 1 kHz: 0 dB data input, using the 20 kHz low-pass filter and the A filter (AD725D built in) LCHP, RCHP, LCHN, RCHN; 1 kHz: 0 dB data input, using the 20 kHz low-pass filter (AD725D built in) 84 min typ 0.008 max 0.010 Unit %
Dynamic range
DR
88
dB
Signal-to-noise ratio
S/N
98
100
dB
Crosstalk
CT
96
98
dB
Note: Measured with the normal-speed playback mode in the Sanyo one-bit D/A converter block reference digital attenuator circuit set to EE (hexadecimal).
Figure 1 Command Input
No. 5223-4/34
LC78621E
Figure 2 Subcode Q Output
Figure 3 Subcode Output
No. 5223-5/34
LC78621E One-Bit D/A Converter Output Block Reference Circuit (normal speed playback)
No. 5223-6/34
LC78621E Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Symbol DEFI TAI PDO VVSS ISET VVDD FR VSS EFMO EFMO EFMIN TEST2 CLV+ CLV- V/P FOCS FST FZD HFL TES PCK FSEQ TOFF TGL THLD TEST3 VDD JP+ JP- DEMO TEST4 EMPH LRCKO DFORO DFOLO DACKO TST10 ASDACK ASDFIN ASDFIR ASLRCK O O I I O O O O O O I I I I Digital filter outputs O O I I O O O O O I I I O O O O O I Slice level control AI AI I/O I I O PLL pins Function Defect detection signal (DEF) input (Must be tied low if unused.) Test input. A pull-down resistor is built in. External VCO control phase comparator output Internal VCO ground. Normally 0 V. PDO output current adjustment resistor connection Internal VCO power supply. VCO frequency range adjustment Digital system ground. Normally 0 V. EFM signal inverted output EFM signal output EFM signal input Test input. A pull-down resistor is built in. Spindle servo control output. Acceleration when CLV+ is high, deceleration when CLV- is high Three-value output is also possible when specified by microprocessor command. Rough servo/phase control automatic switching monitor output. Outputs a high level during rough servo and a low level during phase control. Focus servo on/off output. Focus servo is on when the output is low. Focus start pulse output. This is an open-drain output. Focus error zero cross signal input. (Must be tied low if unused.) Track detection signal input. This is a Schmitt input. Tracking error signal input. This is a Schmitt input. EFM data playback clock monitor. Outputs 4.3218 MHz when the phase is locked. Synchronization signal detection output. Outputs a high level when the synchronization signal detected from the EFM signal and the internally generated synchronization signal agree. Tracking off output Tracking gain switching output. Increase the gain when low. Tracking hold output Test input. A pull-down resistor is built in. Digital system power supply. Track jump output. A high level output from JP+ indicates acceleration during an outward jump or deceleration during an inward jump. A high level output from JP- indicates acceleration during an inward jump or deceleration during an outward jump. Three-value output is also possible when specified by microprocessor command. Sound output function input used for end product adjustment manufacturing steps. A pull-down resistor is built in. Test input. A pull-down resistor is built in. De-emphasis monitor pin. A high level indicates playback of a de-emphasis disk. Word clock output Right channel data output Left channel data output Bit clock output Test output. Leave open. (Normally outputs a low level.) Bit clock input Left/right channel data input Anti-shock system inputs (Must be tied low if unused.) Test input. (Should be tied low for normal operation.) Word clock input
Continued on next page. No. 5223-7/34
LC78621E
Continued from preceding page.
Pin No. 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Symbol LRSY CK2 ROMXA C2F MUTEL LVDD LCHP LCHN LVSS RVSS RCHN RCHP RVDD MUTER DOUT SBSY EFLG PW SFSY SBCK FSX WRQ RWC SQOUT COIN CQCK RES TST11 LASER 16M 4.2M CONT TEST5 CS XVSS XIN XOUT XVDD TEST1 I I O O O O O O O I O O I O I I I O O O O O I I Digital output Subcode block synchronization signal C1, C2, single and double error correction monitor pin Subcode P, Q, R, S, T, U, V and W output Subcode frame synchronization signal output. This signal falls when the subcodes are in the standby state. Subcode readout clock input. This is a Schmitt input. (Must be tied low when unused.) Output for the 7.35 kHz synchronization signal divided from the crystal oscillator Subcode Q output standby output Read/write control input. This is a Schmitt input. Subcode Q output Command input from the control microprocessor Input for both the command input acquisition clock and the SQOUT pin subcode readout clock input. This is a Schmitt input. Chip reset input. This pin must be set low briefly after power is first applied. Test output. Leave open. (Normally outputs a low level.) Laser on/off output. Controlled by serial data commands from the control microprocessor. 16.9344 MHz output. 4.2336 MHz output Supplementary control output. Controlled by serial data commands from the control microprocessor. Test input. A pull-down resistor is built in. Chip select input. A pull-down resistor is built in. Crystal oscillator ground. Normally 0 V. Connections for a 16.9344 MHz crystal oscillator. Crystal oscillator power supply. Test input. A pull-down resistor is built in. O O O O One-bit D/A converter I/O O O O O O ROMXA application output signals Left/right clock output Bit clock output (after reset) Interpolation data output (after reset) C2 flag output Left channel mute output Left channel power supply. Left channel P output Left channel N output Left channel ground. Normally 0 V. Right channel ground. Normally 0 V. Right channel N output Right channel P output Right channel power supply. Right channel mute output Inverted polarity clock output (during CK2CON mode) ROM data output (During ROMXA mode) Function
No. 5223-8/34
LC78621E CD System Block Diagrams
Pin Applications 1. HF Signal Input Circuit; Pin 11: EFMIN, pin 10: EFMO, pin 9: EFMO, pin 1: DEFI, pin 13: CLV+ An EFM signal (NRZ) sliced at an optimal level can be acquired by inputting the HF signal to EFMIN. The LC78621E handles defects as follows. When a high level is input to the DEFI pin (pin 1), the EFMO (pin 9) and EFMO (pin 10) pins (the slice level control outputs) go to the highimpedance state, and the slice level is held. However, note that this function is only valid in CLV phase control mode, that is, when the V/P pin (pin 15) is low. This function can be used in combination with the LA9230M and LA9231M DEF pins. Note: If the EFMIN and CLV+ signal lines are too close to each other, unwanted radiation can result in error rate degradation. We recommend laying a ground or VDD shield line between these two lines. 2. PLL Clock Generation Circuit; Pin 3: PDO, pin 5: ISET, pin 7: FR, pin 21: PCK Since the LC78621E includes a VCO circuit, a PLL circuit can be formed by connecting an external RC circuit. ISET is the charge pump reference current, PDO is the VCO circuit loop filter, and FR is a resistor that determines the VCO frequency range. (Reference values) R1 = 68 k, C1 = 0.1 F R2 = 680 k, C2 = 0.1 F R3 = 1.2 k
3. VCO Monitor; Pin 21: PCK PCK is a monitor pin that outputs an average frequency of 4.3218 MHz, which is divided from the VCO frequency. 4. Synchronization Detection Monitor; Pin 22: FSEQ Pin 22 goes high when the frame synchronization (a positive polarity synchronization signal) from the EFM signal read in by PCK and the timing generated by the counter (the interpolation synchronization signal) agree. This pin is thus a synchronization detection monitor. (It is held high for a single frame.)
No. 5223-9/34
LC78621E 5. Servo command function; Pin 64: RWC, pin 66: COIN, pin 67: CQCK Commands can be executed by setting RWC high and inputting commands to the COIN pin in synchronization with the CQCK clock. Note that commands are executed on the falling edge of RWC. Focus start Track jump Muting control Disk motor control Miscellaneous control Track check Digital attenuator * One-byte commands
One-byte commands
Two-byte command (RWC set twice) Two-byte command (RWC set once)
* Two-byte commands (RWC set twice)
* Two-byte commands (RWC set once)
No. 5223-10/34
LC78621E * Command noise rejection
MSB LSB Command COMMAND INPUT NOISE REDUCTION MODE RESET NOISE EXCLUSION MODE RES = low
11101111 11101110
q
This command reduces the noise on the CQCK clock signal. While this is effective for noise pulses shorter than 500 ns, the CQCK timings TWoL, TWoH, and tsetup (see page 4 and 5, figure 1 and 2), must be set for at least 1 s. 6. Focus Servo Circuit; Pin 16: FOCS, pin 17: FST, pin 18: FZD, pin 70: LASER
MSB LSB Command FOCUS START #1 FOCUS START #2 LASER ON LASER OFF NOTHING RES = low
00001000 10100010 00001010 10001010 11111110
q
The FOCS, FST, and FZD pins are not required when the LC78621E is used in combination with the LA9230M or the LA9231M. FZD should be tied low when these pins are not used. The LA9230M and LA9231M focus start command is identical to the LC78621E FOCUS START #1 command. * NOTHING This command can be used to initialize the LC78621E by inputting FE (hexadecimal). Note that 00 (hexadecimal) is the reset command for the LA9230M and the LA9231M, and should be used with care since it clears the result of the automatic adjustment process and returns these chips to their initial states. * Laser control The LASER pin can be use as an extended output port.
* Focus start When the LC78621E is used in combination with the LA9230M or the LA9231M, the focus start operation is executed completely on the servo side by commands form the control microprocessor. The following section describes this operation when the LC78621E is used in combination with the LA9230M or the LA9231M. When a focus start instruction (either FOCUS START #1 or FOCUS START #2) is input as a servo command, first the charge on capacitor C1 is discharged by FST and the objective lens is lowered. Next, the capacitor is charged by FOCS, and the lens is slowly raised. FZD falls when the lens reaches the focus point. When this signal is received, FOCS is reset and the focus servo turns on. After sending the command, the microprocessor should check the in-focus detection signal (the LA9210 DRF signal) to confirm focus before proceeding to the next part of the program. If focus is not achieved by the time C1 is fully charged, the microprocessor should issue another focus command and iterate the focus servo operation.
No. 5223-11/34
LC78621E
Values in parentheses are for the LASER START #2 command. The only difference is in the FST low period. Note: 1. An FZD falling edge will not be accepted during the period that FST is low. 2. After issuing a focus start command, initialization will be performed if RWC is set high. Therefore, do not issue the next command during focus start until the focus coil drive S curve has completed. 3. When focus cannot be achieved (i.e., when FZD does not go low) the FOCS signal will remain in the high state and the lens will remain raised, so the microprocessor should initialize the system by issuing a NOTHING command. 4. When the RESET pin is set low, the LASER pin is set high directly. 5. Focus start using the DEMO pin executes a mode #1 focus start.
7. CLV servo circuit; Pin 13: CLV+, pin 14: CLV-, pin 15: V/P
MSB LSB Command DISC MOTOR START (accelerate) DISC MOTOR CLV (CLV) DISC MOTOR BRAKE (decelerate) DISC MOTOR STOP (stop) RES = low
00000100 00000101 00000110 00000111
q
The CLV+ pin provides the signal that accelerates the disk in the forward direction and the CLV- pin provides the signal that decelerates the disk. Commands from the control microprocessor select one of four modes; accelerate, decelerate, CLV and stop. The table below lists the CLV+ and CLV- outputs in each of these modes.
Mode Accelerate Decelerate CLV Stop CLV+ High Low * Low CLV- Low High * Low
No. 5223-12/34
LC78621E
Note: CLV servo control commands can set the TOFF pin low only in CLV mode. That pin will be at the high level at all other times. Control of the TOFF pin by microprocessor command is only valid in CLV mode. * CLV mode In CLV mode the LC78621E detects the disk speed from the HF signal and provides proper linear speed using several different control schemes by switching the DSP internal modes. The PWM reference period corresponds to a frequency of 7.35 kHz. The V/P pin outputs a high level during rough servo and a low level during phase control.
Internal mode Rough servo (velocity too low) Rough servo (velocity too high) Phase control (PCK locked) CLV+ High Low PWM CLV- Low High PWM V/P High High Low
* Rough servo gain switching
MSB LSB Command DISC 8 SET DISC 12 SET RES = low
10101000 10101001
q
For 8 cm disks, the rough servo mode CLV control gain can be set about 8.5 dB lower than the gain used for 12 cm disks. * Phase control gain switching
MSB LSB Command CLV PHASE COMPARATOR DIVISOR: 1/2 CLV PHASE COMPARATOR DIVISOR: 1/4 CLV PHASE COMPARATOR DIVISOR: 1/8 NO CLV PHASE COMPARATOR DIVISOR USED RES = low
10110001 10110010 10110011 10110000
q
The phase control gain can be changed by changing the divisor used by the dividers in the stage immediately preceding the phase comparator.
No. 5223-13/34
LC78621E * CLV three value output
MSB LSB Command CLV THREE VALUE OUTPUT CLV TWO VALUE OUTPUT (the scheme used by previous products) RES = low
10110100 10110101
q
The CLV three value output command allows the CLV to be controlled by a single pin.
* Internal brake modes
MSB LSB Command INTERNAL BRAKE ON INTERNAL BRAKE OFF INTERNAL BRAKE CONT INTERNAL BRAKE CONTINUOUS MODE RESET CONTINUOUS MODE TON MODE DURING INTERNAL BRAKING RESET TON MODE RES = low
11000101 11000100 10100011 11001011 11001010 11001101 11001100
q
q q
-- Issuing the internal brake-on (C5H) command sets the LC78621E to internal brake mode. In this mode, the disk deceleration state can be monitored from the WRQ pin when a brake command (06H) is executed. -- In this mode the disk deceleration state is determined by counting the EFM signal density in a single frame, and when the EFM signal count falls under four, the CLV- pin is dropped to low. At the same time the WRQ signal, which functions as a brake completion monitor, goes high. When the microprocessor detects a high level on the WRQ signal, it should issue a STOP command to fully stop the disk. In internal brake continuous mode, the CLV- pin high-level output braking operation continues even after the WRQ brake completion monitor goes high. Note that if errors occur in deceleration state determination due to noise in the EFM signal, the problem can be rectified by changing the EFM signal count from four to eight with the internal brake control command (A3H). -- In internal braking TON mode, the TOFF pin is held low during internal brake operations. We recommend using this feature, since it is effective at preventing incorrect detection at the disk mirror surface.
No. 5223-14/34
LC78621E
Note: 1. If focus is lost during the execution of an internal brake command, the pickup must first be refocussed and then the internal brake command must be reissued. 2. Since incorrect deceleration state determination is possible depending on the EFM signal playback state (e.g., disk defects, access in progress), we recommend using these functions in combination with a microprocessor. 8. Track Jump Circuit; Pin 19: HFL, pin 20: TES, pin 23: TOFF, pin 24: TGL, pin 25: THLD, pin 28: JP+, pin 29: JP- * The LC78621E supports the two track count modes listed below.
MSB LSB Command NEW TRACK COUNT (using the TES/HFL combination) STANDARD TRACK COUNT (directly counts the TES signal) RES = low
00100010 00100011
q
The earlier track count function uses the TES signal directly as the internal track counter clock. To reduce counting errors resulting from noise on the rising and falling edges of the TES signal, the new track count function prevents noise induced errors by using the combination of the TES and HFL signals, and implements a more reliable track count function. However, dirt and scratches on the disk can result in HFL signal dropouts that may result in missing track count pulses. Thus care is required when using this function.
No. 5223-15/34
LC78621E * TJ commands
MSB LSB Command STANDARD TRACK JUMP NEW TRACK JUMP 1 TRACK JUMP IN #1 1 TRACK JUMP IN #2 1 TRACK JUMP IN #3 1 TRACK JUMP IN #4 2 TRACK JUMP IN 4 TRACK JUMP IN 16 TRACK JUMP IN 32 TRACK JUMP IN 64 TRACK JUMP IN 128 TRACK JUMP IN 1 TRACK JUMP OUT #1 1 TRACK JUMP OUT #2 1 TRACK JUMP OUT #3 1 TRACK JUMP OUT #4 2 TRACK JUMP OUT 4 TRACK JUMP OUT 16 TRACK JUMP OUT 32 TRACK JUMP OUT 64 TRACK JUMP OUT 128 TRACK JUMP OUT 256 TRACK CHECK TOFF TON TRACK JUMP BRAKE THLD PERIOD TOFF OUTPUT MODE RESET THLD PERIOD TOFF OUTPUT MODE RES = low
10100000 10100001 00010001 00010010 00110001 01010010 00010000 00010011 00010100 00110000 00010101 00010111 00011001 00011010 00111001 01011010 00011000 00011011 00011100 00111000 00011101 00011111 00010110 00001111 10001111 10001100 00100001 00100000
q
q
q
When the LC78621E receives a track jump instruction as a servo command, it first generates accelerating pulses (period a) and next generates deceleration pulses (period b). The passage of the braking period (period c) completes the specified jump. During the braking period, the LC78621E detects the beam slip direction from the TES and HFL inputs. TOFF is used to cut the components in the TE signal that aggravate slip. The jump destination track is captured by increasing the servo gain with TGL. In THLD period TOFF output mode the TOFF signal is held high during the period when THLD is high. Note: Of the modes related to disk motor control, the TOFF pin only goes low in CLV mode, and will be high during start, stop, and brake operations. Note that the TOFF pin can be turned on and off independently by microprocessor issued commands. However, this function is only valid when disk motor control is in CLV mode.
No. 5223-16/34
LC78621E * Track jump modes The table lists the relationships between acceleration pulses, deceleration pulses, and the braking period.
Command 1 TRACK JUMP IN (OUT) #1 1 TRACK JUMP IN (OUT) #2 1 TRACK JUMP IN (OUT) #3 233 s 0.5 track jump period 0.5 track jump period 0.5 track jump period None 2 track jump period 9 track jump period 18 track jump period 36 track jump period 72 track jump period Standard track jump mode a 233 s 233 s 233 s b 60 ms 60 ms This period does not exist. 60 ms; TOFF is low during the C period. None 60 ms 60 ms 60 ms 60 ms 60 ms c 233 s 0.5 track jump period 0.5 track jump period 0.5 track jump period 1 track jump period 2 track jump period 9 track jump period 18 track jump period 36 track jump period 72 track jump period a 233 s 0.5 track jump period 0.5 track jump period 0.5 track jump period 1 track jump period 2 track jump period 9 track jump period 14 track jump period 28 track jump period 56 track jump period New track jump mode b 60 ms 60 ms This period does not exist. 60 ms; TOFF is low during the C period. This period does not exist. 60 ms 60 ms 60 ms 60 ms 60 ms c
1 TRACK JUMP IN (OUT) #4
233 s
2 TRACK JUMP IN (OUT) 4 TRACK JUMP IN (OUT) 16 TRACK JUMP IN (OUT) 32 TRACK JUMP IN (OUT) 64 TRACK JUMP IN (OUT) 128 TRACK JUMP IN (OUT)
None 466 s 7 track jump period 14 track jump period 28 track jump period 56 track jump period
256 TRACK CHECK TRACK JUMP BRAKE
TOFF goes high during the period when 256 tracks are passed over. The a and b pulses are not output. There are no a or b periods.
60 ms 60ms
TOFF goes high during the period when 256 tracks are passed over. The a and b pulses are not output. There are no a and b periods.
60 ms 60 ms
Note: 1. As indicated in the table, actuator signals are not output during the 256 TRACK CHECK function. This is a mode in which the TES signal is counted in the tracking loop off state. Therefore, feed motor forwarding is required. 2. The servo command register is automatically reset after one cycle of the track jump sequence (a, b, c) completes. 3. If another track jump command is issued during a track jump operation, the content of that new command will be executed starting immediately. 4. The 1 TRACK JUMP #3 and 2 TRACK JUMP modes do not have a braking period (the C period). Since brake mode must be generated by an external circuit, care is required when using this mode.
When the LC78621E is used in combination with the LA9230M or the LA9231M, since the THLD signal is generated by the LA9230M or the LA9231M, the THLD pin (pin 25) will be unused, i.e., have no connection. 5. Tracking brake The chart shows the relationships between the TES, HFL, and TOFF signals during the track jump C period. The TOFF signal is extracted from the HFL signal by TES signal edges. When the HFL signal is high, the pickup is over the mirror surface, and when low, the pickup is over data bits. Thus braking is applied based on the TOFF signal being high when the pickup is moving from a mirror region to a data region and being low when the pickup is moving from a data region to a mirror region.
No. 5223-17/34
LC78621E * JP three-value output
MSB LSB Command JP THREE VALUE OUTPUT JP TWO VALUE OUTPUT (earlier scheme) RES = low
10110110 10110111
q
The JP three-value output command allows the track jump operation to be controlled from a single pin.
* Track check mode
MSB LSB Command TRACK CHECK IN TRACK CHECK OUT TWO BYTE COMMAND RESET RES = low
11110000 11111000 11111111
q
The LC78621E will count the specified number of tracks minus one when the microprocessor sends an arbitrary binary value in the range 8 to 254 after issuing either a track check in or a track check out command.
Note: 1. When the desired track count has been input in binary, the track check operation is started by the fall of RWC. 2. During a track check operation the TOFF pin goes high and the tracking loop is turned off. Therefore, feed motor forwarding is required. 3. When a track check in/out command is issued the function of the WRQ signal switches from the normal mode subcode Q standby monitor function to the track check monitor function. This signal goes high when the track check is half completed, and goes low when the check finishes. The control microprocessor should monitor this signal for a low level to determine when the track check completes. 4. If a two-byte reset command is not issued, the track check operation will repeat. That is, to skip over 20,000 tracks, issue a track check 201 command once, and then count the WRQ signal 100 times. This will check 20,000 tracks. 5. After performing a track check operation, use the brake command to have the pickup lock onto the track.
No. 5223-18/34
LC78621E 9. Error Flag Output; Pin 58: EFLG, pin 62: FSX
The FSX signal is generated by dividing the crystal oscillator clock, and is a 7.35 kHz frame synchronization signal. The error correction state for each frame is output from EFLG. The playback OK/NG state can be easily determined from the extent of the high level that appears here. 10. Subcode P, Q, and R to W Output Circuit; Pin 59: PW, pin 57: SBSY, pin 60: SFSY, pin 61: SBCK PW is the subcode signal output pin, and all the codes, P, Q, and R to W can be read out by sending eight clocks to the SBCK pin within 136 s after the fall of SFSY. The signal that appears on the PW pin changes on the falling edge of SBCK. If a clock is not applied to SBCK, the P code will be output from PW. SFSY is a signal that is output for each subcode frame cycle, and the falling edge of this signal indicates standby for the output of the subcode symbol (P to W). Subcode data P is output on the fall of this signal.
SBSY is a signal output for each subcode block. This signal goes high for the S0 and S1 synchronization signals. The fall of this signal indicates the end of the subcode synchronization signals and the start of the data in the subcode block. (EIAJ format)
No. 5223-19/34
LC78621E 11. Subcode Q Output Circuit; Pin 63: WRQ, pin 64: RWC, pin 65: SQOUT, pin 67: CQCK, pin 75: CS
MSB LSB Command ADDRESS FREE ADDRESS 1 RES = low
00001001 10001001
q
Subcode Q can be read from the SQOUT pin by applying a clock to the CQCK pin. Of the eight bits in the subcode, the Q signal is used for song (track) access and display. The WRQ will be high only if the data passed the CRC error check and the subcode Q format internal address is 1*. The control microprocessor can read out data from SQOUT in the order shown below by detecting this high level and applying CQCK. When CQCK is applied the DSP disables register update internally. The microprocessor should give update permission by setting RWC high briefly after reading has completed. WRQ will fall to low at this time. Since WRQ falls to low 11.2 ms after going high, CQCK must be applied during the high period. Note that data is read out in an LSB first format. Note: * That state will be ignored if an address free command is input. This is provided to handle CD-ROM applications.
Note: 1. Normally, the WRQ pin indicates the subcode Q standby state. However, it is used for a different monitoring purpose in track check mode and during internal braking. (See the items on track counting and internal braking for details.) 2. The LC78621E becomes active when the CS pin is low, and subcode Q data is output from the SQOUT pin. When the CS pin is high, the SQOUT pin goes to the high-impedance state.
No. 5223-20/34
LC78621E 12. Level Meter (LVM) Data and Peak Meter (PKM) data readout
MSB LSB Command PKM SET (LVM Reset) LVM SET (PKM Reset) PKM MASK SET PKM MASK RESET RES = low
00101011 00101100 00101101 00101110
q q
* Level meter (LVM) -- The LVM set (2CH) command sets the LC78621E to LVM mode. -- LVM data is a 16-bit word in which the MSB indicates the L/R polarity and the low-order 15 bits are absolute value data. A one in the MSB indicates left channel data and a zero indicates right channel data. -- LVM data is appended after the 80 bits of SubQ data, and can be read out by applying 96 clock cycles to the CQCK pin. Each time LVM data is read out the left/right channel state is inverted. Data is held independently for both the left and right channels. In particular, the largest value that occurs between readouts for each channel is held. * Peak meter (PKM) -- The PKM set (2BH) command sets the LC78621E to PKM mode. -- PKM data is a 16-bit word in which the MSB is always zero and the low-order 15 bits are absolute value data. This functions detects the maximum value that occurs in the data, whichever channel that value occurs in. -- PKM data is read out in the same manner as LVM data. However, data is not updated as a result of the readout operation. -- The absolute time for PKM mode SubQ data is computed by holding the absolute time (ATIME) detected after the maximum value occurred and sending that value. (Normal operation uses relative time.) -- It is possible to set the LC78621E to ignore values larger than the already recorded value by issuing the PKM mask set command, even in PKM mode. This function is cleared by issuing a PKM mask reset command. (This is used in PK search in a memory track.) 13. Mute Control Circuit
MSB LSB Command MUTE: 0 dB MUTE: -12 dB MUTE: - dB RES = low
00000001 00000010 00000011
q
An attenuation of 12 dB (MUTE -12 dB) or full muting (MUTE dB) can be applied by issuing the appropriate command from the table. Since zero cross muting is used, there is minimal noise associated with this function. Zero cross is defined for this function as the top seven bits being all ones or all zeros.
No. 5223-21/34
LC78621E 14. Interpolation Circuit Outputting incorrect audio data that could not be corrected by the error detection and correction circuit would result in loud noises being output. To minimize this noise, the LC78621E replaces the incorrect data with linearly interpolated data based on the correct data on either side of the incorrect data. More precisely, the LC78621E uses this technique if C2 flags occurred up to three times in a row. If C2 flags occurred four or more times in a row, the LC78621E converges the output level to the muting level. However, when correct data is finally output following four or more C2 flag occurrences, the LC78621E replaces the 3 data items between the data output three items previously and the correct data with data linearly interpolated data.
15. Bilingual Function
MSB LSB Command STO CONT Lch CONT Rch CONT RES = low
00101000 00101001 00101010
q
* Following a reset or when a stereo (28H) command has been issued, the left and right channel data is output to the left and right channels respectively. * When an Lch set (29H) command is issued, the left and right channels both output the left channel data. * When an Rch set (2AH) command is issued, the left and right channels both output the right channel data. 16. De-Emphasis; Pin 32: EMPH The preemphasis on/off bit in the subcode Q control information is output from the EMPH pin. When this pin is high, the LC78621E internal de-emphasis circuit operates and the digital filters and the D/A converter output deemphasized data. 17. Digital Attenuator Digital attenuation can be applied to the audio data by setting the RWC pin high and inputting the corresponding two-byte command to the COIN pin in synchronization with the CQCK clock.
MSB LSB Command ATT DATA SET ATT 4 STEP UP ATT 4 STEP DOWN ATT 8 STEP UP ATT 8 STEP DOWN ATT 16 STEP UP ATT 16 STEP DOWN RES = low DATA 00H set (MUTE - dB)
10000001 10000010 10000011 10000100 10000101 10000110 10000111
No. 5223-22/34
LC78621E * Attenuation setup Since the attenuation level is set to the muted state (a muting of - is specified by an attenuation coefficient of 00H) after the attenuation level is reset, the attenuation coefficient must be directly set to EEH (using the ATT DATA SET command) to output audio signals. Note that the attenuation level can be set to one of 239 values from 00H to EEH. These two-byte commands differ from the two-byte commands used for track counting in that it is only necessary to set RWC once and a two-byte command reset is not required. (See the item on two-byte commands (RWC set once) on page 10.)
After inputting the target attenuation level as a value in the range 00H to EEH, sending an attenuator step up/down command will cause the attenuation level to approach the target value in steps of 4, 8, or 16 units as specified in synchronization with rising edges on the LRSY input. However, the ATT DATA SET command sets the target value directly. If a new data value is input during the transition, the value begins to approach the new target value at that point. Note that the UP/DOWN distinction is significant here.
Audio output level = 20 log
ATT DATA [dB] 100H
For example, the formula below calculates the time required for the attenuation level to increase from 00H to EEH when a 4STEP UP command is executed. Note that the control microprocessor must provide enough of a time margin for this operation to complete before issuing the next attenuation level set command. 238 level x 4STEP UP 21.6 ms 44.1 kHz (LRSY) Note: Setting the attenuation level to values of EFH or higher is disallowed to prevent overflows in one-bit D/A converter calculations from causing noise. * Mute output; Pin 46: MUTEL, pin 55: MUTER These pins output a high level when the attenuator coefficient is set to 00H and the data in each channel has been zero for a certain period. If data input occurs once again, these pins go low immediately.
No. 5223-23/34
LC78621E 18. Digital Filter Outputs; Pin 33: LRCKO, pin 34: DFORO, pin 35: DFOLO, pin 36: DACKO Data for use with an external D/A converter is output MSB first from DFORO and DFOLO in synchronization with the falling edge of DACKO. These pins are provided so that an external D/A converter can be used if desired.
* Although this output is from 8x oversampling filters for normal-speed playback, 4x oversampling filters are used in double-speed playback. 19. One-bit D/A Converter * The LC78621E PWM block outputs a single data value in the range -3 to +3 once every 64fs period. To reduce carrier noise, this block adopts an output format in which each data switching block is adjusted so that the PWM output level does not invert. Also, the attenuator block detects 0 data and enters muting mode so that only a 0 value (a 50% duty signal) is output. This block outputs a positive phase signal to the LCHP (RCHP) pin and a negative phase signal to the LCHN (RCHN) pin. High-quality analog signals can be acquired by taking the differences of these two output pairs using external low-pass filters. The LC78621E includes built-in suppression resistors in each of the LCHP/N and RCHP/N pins. * PWM output format
* PWM output example
No. 5223-24/34
LC78621E 20. CD-ROM Outputs; Pin 42: LRSY, pin 43: CK2, pin 44: ROMXA, pin 45: C2F Although the LC78621E is initially set up to output audio data from the interpolation circuit MSB first from the ROMXA pin in synchronization with the LRSY signal, the circuit can be switched to output CD-ROM data by issuing a CD-ROM XA command. Since this data has not been processed by the interpolation, muting, and other digital circuits, it is appropriate for input to a CD-ROM encoder LSI. CK2 is a 2.1168 MHz clock, and data is output on the CK2 falling edge. However, this clock polarity can be inverted by issuing a CK2 polarity inversion command. C2F is the flag information for the data in 8-bit units. Note that the CD-ROM XA reset command has the same function as the CONT pin (pin 73).
MSB LSB Command CD-ROM XA CONT AND CD-ROM XA RESET CK2 POLARITY INVERSION RES = low
10001000 10001011 11001001
q
LC78621E CD-ROM encoder LSI (LC895XX) interface
21. Digital Output Circuit; Pin 56: DOUT This is an output pin for use with a digital audio interface. Data is output in the EIAJ format. This signal has been processed by the interpolation and muting circuits. This pin has a built-in driver circuit and can directly drive a transformer.
MSB LSB Command DOUT ON DOUT OFF UBIT ON UBIT OFF RES = low
01000010 01000011 01000000 01000001
q q
* The DOUT pin can be locked at the low level by issuing a DOUT OFF command. * The UBIT information in the DOUT data can be locked at zero by issuing a UBIT OFF command. * The DOUT data can be switched to data for which interpolation and muting processing have not been performed by issuing a CD-ROM XA command. 22. AntiShock Mode; Pin 38: ASDACK, pin 39: ASDFIN, pin 40: ASDFIR, pin 41: ASLRCK, pin 42: LRSY, pin 43: CK2, pin 44: ROMXA, pin 45: C2F * Antishock mode is a mode in which antishock processing is applied to data that has been output once. That data is returned and output once again as an audio playback signal. It is also possible to use only the audio playback block (the attenuator, 8x oversampling digital filter, and one-bit D/A converter circuits) and thus share the audio playback block with other systems by synchronizing the other system with this LSI's clock. Note that de-emphasis on/off switching is controlled by the LC78621E subcode Q playback state.
No. 5223-25/34
LC78621E * The ASDACK (pin 38), ASDFIN (pin 39), ASDFIR (pin 40), and ASLRCK (pin 41) pins must be held low if this mode is not used.
MSB LSB ANTIC ON ANTIC OFF DF NORMAL SPEED ON (only in antishock mode) DF NORMAL SPEED OFF (only in antishock mode) Command RES = low
01101100 01101011 01101111 01101110
q q
* It is possible to input the signals from the ROMXA (pin 44), C2F (pin 45), LRSY (pin 42), and CK2 (pin 43) pins to an antishock LSI (the Sanyo LC89151) and re-input the signals output by the antishock LSI to the ASDFIN (pin 39), ASLRCK (pin 41), and ASDACK (pin 38) pins. These signals are then processed by the attenuator, 8x oversampling digital filter, and one-bit D/A converter circuits and output as audio signals. * In antishock systems, the signal-processing block must operate in double-speed playback mode for data output to the antishock LSI, and the audio playback block (the attenuator, 8x oversampling digital filter, and one-bit D/A converter circuits) must operate at normal speed. This means that the control microprocessor must issue both the ANTIC on command (6CH) as well as the DF normal speed on command (6FH). * The ANTIC off command (6BH) clears antishock mode.
23. CONT Pin; Pin 73: CONT
MSB LSB Command CONT SET CONT AND CD-ROM XA RESET RES = low Low
00001110 10001011
q
The CONT pin goes high when a CONT SET command is issued. 24. Clock Oscillator; Pin 77: XIN, pin 78: XOUT
MSB LSB OSC ON OSC OFF NORMAL-SPEED PLAYBACK DOUBLE-SPEED PLAYBACK Command RES = low 10001110 10001101 11000010 11000001
q q
The clock that is used as the time base is generated by connecting a 16.9344 MHz oscillator element between these pins. The OSC OFF command turns off both the VCO and crystal oscillators. Double-speed playback can be specified by microprocessor command.
No. 5223-26/34
LC78621E * Recommended crystal and ceramic oscillator elements
Manufacturer Citizen Watch Co., Ltd. (crystal oscillator elements) TDK, Ltd. (ceramic oscillator elements) Product No. Load capacitance C1/C2 (C1 = C2) 6 pF to 10 pF (10%) 15 pF (10%) 30 pF (Includes built-in capacitors) 0 100 (10%) 47 (10%) Damping resistor Rd
CSA-309 (16.9344 MHz) FCR 16.93M2G (16.93 MHz) FCR 16.93MCG (16.93 MHz)
Since the conditions for the load capacitors Cin and Cout used varies with the printed circuit board, this circuit must be tested on the printed circuit board actually used. 25. 16M and 4.2M Pins; Pin 71: 16M, pin 72: 4.2M In normal- and double-speed playback modes, the 16M pin buffer outputs the 16.9344 MHz external crystal oscillator 16.9344 MHz signal. The 4.2M pin supplies the LA9231M or LA9231M system clock, normally outputting a 4.2336 MHz signal. When the oscillator is turned off both these pins will be fixed at either high or low.
No. 5223-27/34
LC78621E 26. Reset Circuit; Pin 68: RES When power is first applied, this pin should be briefly set low and then set high. This will set the muting to - dB and stop the disk motor.
Constant linear velocity servo Muting control Q subcode address conditions Laser control CONT Track jump mode Track count mode Digital attenuator OSC Playback speed Anti-shock mode Digital filter normal speed START 0 dB Address 1 ON (low) High Standard Standard DATA 0 ON Normal speed ON ON OFF Double speed OFF OFF STOP -12 db Address free OFF Low New New DATA 00H to EEH (high) BRAKE CLV
-
Setting the RES pin low sets the LC78621E to the settings enclosed in boxes in the table.
27. Adjustment Process Sound Output Function; Pin 30: DEMO
No. 5223-28/34
LC78621E The DEMO pin can be used when the LC78621E is used in combination with an LA9210M or LA9211M. By setting this pin high, muting can be set to 0 dB, the disk motor can be set to CLV, and a focus start operation can be performed, even without issuing any commands from the control microprocessor. Also, since the LASER pin becomes active, if the mechanism and servo systems are complete, an EFM signal can be acquired with only this equipment, and an audio signal can be produced without the presence of a microprocessor. However, since the digital attenuation is set to 100H, this technique is not appropriate for evaluating audio quality. 28. Other Pins; Pin 2:TAI, pin 80: TEST1, pin 12: TEST2, pin 26: TEST3, pin 31: TEST4, pin 74: TEST5, pin 40: ASDFIR These pins are used for testing the LSI's internal circuits. Since the pins TAI and TEST1 to TEST5 have built-in pull-down resistors, they can be left open in normal operation. ASDFIR must be connected to ground in normal operation. 29. Circuit Block Operating Descriptions * RAM address control The LC78621E incorporates an 8-bit x 2k-word RAM on chip. This RAM has an EFM demodulated data jitter handling capacity of 4 frames implemented using address control. The LC78621E continuously checks the remaining buffer capacity and controls the data write address to fall in the center of the buffer capacity by making fine adjustments to the frequency divisor in the PCK side of the CLV servo circuit. If the 4 frame buffer capacity is exceeded, the LC78621E forcibly sets the write address to the 0 position. However, since the errors that occur due to this operation cannot be handled with error flag processing, the IC applies muting to the output for a 128 frame period.
Position -4 or less -3 -2 -1 0 +1 +2 +3 +4 or more Division ratio or processing Force to 0 589 589 589 588 587 587 587 Force to 0 Decrease ratio Standard ratio Increase ratio
No. 5223-29/34
LC78620E * C1 and C2 Error Correction The LC78621E writes EFM demodulated data to internal RAM to compensate for jitter and then performs the following processing with uniform timing based on the crystal oscillator clock. First, the LC78621E performs C1 error checking and correction in the C1 block, determines the C1 flags, and writes the C1 flag register. Next, the LC78621E performs C2 error checking and correction in the C2 block, determines the C2 flags, and writes data to internal RAM.
C1 flag No errors 1 error 2 errors 3 errors or more C2 flag No errors 1 error 2 errors 3 errors or more Error correction and flag processing No correction required * Flag reset Correction * Flag reset Correction * Flag set Correction not possible * Flag set Error correction and flag processing No correction required * Flag reset Correction * Flag reset Depends on C1 flags*1 Depends on C1 flags*2
Note: 1. If the positions of the errors determined by the C2 check agree with those specified by the C1 flags, the correction is performed and the flags are cleared. However, if the number of C1 flags is 7 or higher, C2 correction may fail. In this case correction is not performed and the C1 flags are taken as the C2 flags without change. Error correction is not possible if one error position agrees and the other does not. Furthermore, if the number of C1 flags is 5 or under, the C1 check result can be seen as unreliable. Accordingly, the flags will be set in this case. Cases where the number of C1 flags is 6 or more are handled in the same way, and the C1 flags are taken as the C2 flags without change. When there is not even one agreement between the error positions, error correction is, of course, impossible. Here, if the number of C1 flags was 2 or under, data that was seen as correct after C1 correction is now seen as incorrect data. The flags are set in this case. In other cases, the C1 flags are taken as the C2 flags without change. 2. When data is determined to have three or more errors and be uncorrectable, correction is, of course, impossible. Here, if the number of C1 flags was 2 or under, data that was seen as correct after C1 correction is now seen as incorrect data. The flags are set in this case. In other cases the C1 flags are taken as the C2 flags without change
No. 5130-30/34
LC78621E 30. Command Summary Table Blank entry: Illegal command, #: Changed or added command, *: latching commands (mode setting commands), q : Commands shared with an ASP (LA9230M/31M or other processor), Items in parentheses are ASP commands (provided for reference purposes)
00000000 (ADJ.reset) 0 dB -12 dB - dB 0 0 1 0 0 0 0 0 * TOFF low in TJ mode 0 0 1 0 0 0 0 1 * TOFF high in TJ mode 0 0 1 0 0 0 1 0 * New TRACK COUNT 0 0 1 0 0 0 1 1 * Old TRACK COUNT 01000000 01000001 01000010 01000011 01000100 01000101 01000110 01000111 01001000 01001001 01001010 01001011 01001100 01001101 01001110 01001111 * UBIT ON * UBIT OFF * DOUT ON * DOUT OFF 01100000 01100001 01100010 01100011 01100100 01100101 01100110 01100111 01101000 01101001 01101010 0 1 1 0 1 0 1 1 * #ANTIC off 0 1 1 0 1 1 0 0 * #ANTIC on 01101101 0 1 1 0 1 1 1 0 * #DF normal speed off 0 1 1 0 1 1 1 1 * #DF normal speed on 00010000 00010001 00010010 00010011 00010100 00010101 00010110 00010111 00011000 00011001 00011010 00011011 00011100 00011101 00011110 00011111 128TJ OUT 2TJ 1TJ 1TJ 4TJ 16TJ 64TJ 256TC 128TJ IN 2TJ 1TJ 1TJ 4TJ 16TJ 64TJ OUT OUT #1 OUT #2 OUT OUT OUT IN IN #1 IN #2 IN IN IN 00110000 00110001 00110010 00110011 00110100 00110101 00110110 00110111 00111000 00111001 00111010 00111011 00111100 00111101 00111110 00111111 32TJ 1TJ OUT OUT #3 32TJ 1TJ IN IN #3 01010000 01010001 01010010 01010011 01010100 01010101 01010110 01010111 01011000 01011001 01011010 01011011 01011100 01011101 01011110 01011111 1TJ OUT #4 1TJ IN #4 01110000 01110001 01110010 01110011 01110100 01110101 01110110 01110111 01111000 01111001 01111010 01111011 01111100 01111101 01111110 01111111
0 0 0 0 0 0 0 1 * MUTE 0 0 0 0 0 0 1 0 * MUTE 0 0 0 0 0 0 1 1 * MUTE
0 0 0 0 0 1 0 0 * DISC MTR START 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 1 * DISC MTR CLV 0 0 0 0 0 1 1 1 * DISC MTR STOP 0 0 0 0 1 0 0 0 q FOCUS START #1 0 0 0 0 1 0 0 1 * ADDRESS FREE 0 0 0 0 1 0 1 0 * LASER ON 00001011 00001100 00001101 0 0 0 0 1 1 1 0 * CONT SET 0 0 0 0 1 1 1 1 * TRACKING OFF 00100101 0 0 0 0 0 1 1 0 * DISC MTR BRAKE 0 0 1 0 0 1 1 0 00100111 0 0 1 0 1 0 0 0 * STO CONT 0 0 1 0 1 0 0 1 * LCH CONT 0 0 1 0 1 0 1 0 * RCH CONT 0 0 1 0 1 0 1 1 * PKM SET 0 0 1 0 1 1 0 0 * LVM SET 0 0 1 0 1 1 0 1 * PKM MSK SET 0 0 1 0 1 1 1 0 * PKM MSK RESET 00101111
Continued on next page. No. 5223-31/34
LC78621E
Continued from preceding page.
Blank entry: Illegal command, #: Changed or added command, *: latching commands (mode setting commands), q : Commands shared with an ASP (LA9230M/31M or other processor), Items in parentheses are ASP commands (provided for reference purposes)
1 0 0 0 0 0 0 0 * #ATT 0 dB SET 1 0 0 0 0 0 0 1 * #ATT DATA SET 1 0 0 0 0 0 1 0 * #ATT 4STP UP 1 0 0 0 0 0 1 1 * #ATT 4STP DWN 1 0 0 0 0 1 0 0 * #ATT 8STP UP 1 0 0 0 0 1 0 1 * #ATT 8STP DWN 1 0 0 0 0 1 1 0 * #ATT 16STP UP 1 0 0 0 1 0 0 0 * CDROMXA 1 0 0 0 1 0 0 1 * ADDRESS 1 1 0 0 0 1 0 1 0 * LASER OFF 1 0 0 0 1 0 1 1 * CONT, ROMXA RST 10001100 TRACK JMP BRK 1 0 1 0 0 0 0 0 * Old TRK JMP 1 0 1 0 0 0 0 1 * New TRK JMP 10100010 FOCS START #2 11000000 11000001 11000010 11000011 11000100 11000101 11000110 11000111 11001000 11001001 11001010 11001011 11001100 11001101 11001110 11001111 * #CK2 polarity inverted * Internal BRK OFF * Internal BRK ON * Double-speed playback * Normal-speed playback 11100000 11100001 11100010 11100011 11100100 11100101 11100110 11100111 11101000 11101001
1 0 1 0 0 0 1 1 * Internal BRKE CONT 10100100 10100101 10100110
1 0 0 0 0 1 1 1 * #ATT 16STP DWN 1 0 1 0 0 1 1 1 1 0 1 0 1 0 0 0 * DISC 8 SET 1 0 1 0 1 0 0 1 * DISC 12 SET 10101010 10101011 10101100 10101101 10101110 10101111
* Internal BRK-DMC 1 1 1 0 1 0 1 0 low * Internal BRK-DMC 1 1 1 0 1 0 1 1 high * TOFF during internal BRK * TON during internal BRK 11101100 11101101 1 1 1 0 1 1 1 0 * Command noise OFF 1 1 1 0 1 1 1 1 * Command noise ON 1 1 1 1 0 0 0 0 * q TRCK CHECK IN (2BYTEDETECT) 11110001 11110010 11110011 11110100 11110101 11110110 11110111 1 1 1 1 1 0 0 0 * q TRCK CHECK OUT (2BYTE DETECT) 11111001 11111010 11111011 11111100 11111101 1 1 1 1 1 1 1 0 # q NOTHING 1 1 1 1 1 1 1 1 * q 2BYTE CMD RST
1 0 0 0 1 1 0 1 * OSC OFF 1 0 0 0 1 1 1 0 * OSC ON 1 0 0 0 1 1 1 1 * TRACKING ON
1 0 0 1 0 0 0 0 (* F.OFF.ADJ.ST)
1 0 1 1 0 0 0 0 * CLV-PH 1/1 mode
11010000
1 0 0 1 0 0 0 1 (* F.OFF.ADJ.OFF) 1 0 0 1 0 0 1 0 (* T.OFF.ADJ.ST) 1 0 0 1 0 0 1 1 (* T.OFF.ADJ.OFF) 1 0 0 1 0 1 0 0 (* LSR.ON)
1 0 1 1 0 0 0 1 * CLV-PH 1/2 mode 1 0 1 1 0 0 1 0 * CLV-PH 1/4 mode 1 0 1 1 0 0 1 1 * CLV-PH 1/8 mode
11010001 11010010 11010011
1 0 1 1 0 1 0 0 * CLV3ST output ON 1 1 0 1 0 1 0 0 11010101 11010110
1 0 0 1 0 1 0 1 (* LSR.OF/F.SV.ON) 1 0 1 1 0 1 0 1 * CLV3ST output OFF 1 0 0 1 0 1 1 0 (* LSR.OF/F.SV.OF) 1 0 1 1 0 1 1 0 * JP3ST output ON 1 0 0 1 0 1 1 1 (* SP.8CM) 1 0 0 1 1 0 0 0 (* SP.12CM) 10111000
1 0 1 1 0 1 1 1 * JP3ST output OFF 1 1 0 1 0 1 1 1 11011000
1 0 0 1 1 0 0 1 (* SP.OFF) 1 0 0 1 1 0 1 0 (* SLED.ON) 1 0 0 1 1 0 1 1 (* SLED.OFF) 1 0 0 1 1 1 0 0 (* EF.BAL.START) 1 0 0 1 1 1 0 1 (* T.SERVO.OFF) 1 0 0 1 1 1 1 0 (* T.SERVO.ON) 10011111
10111001 10111010 10111011 10111100 10111101 10111110 10111111
11011001 11011010 11011011 11011100 11011101 11011110 11011111
No. 5223-32/34
LC78621E 31. Sample Application Circuit
No. 5223-33/34
LC78621E 32. CD-DSP Functional Comparison
Product Function EFM-PLL 16 KRAM Digital output Interpolation Zero-cross muting Level meter Peak meter Bilingual Digital attenuator 2fs 4fs 8fs Digital de-emphasis 1 bit DAC LC7860KA LC7861NE LC7861KE LC7867E LC7868E LC7868KE When paired with an analog ASP q q 4 q q q ! -- q -- q ! LC7869E LC78681E LC78681KE LC78621E Built-in VCO q q 4 q q q q -- -- q q q
When paired with When paired with When paired with an analog ASP an analog ASP an analog ASP External ! 2 ! ! ! ! q -- -- ! ! q q 4 q ! ! ! q -- -- ! ! q q 4 q ! ! ! -- -- -- ! !
When paired with When paired with an analog ASP an analog ASP q q 4 q q q ! -- -- q q ! q q 4 q q q ! -- -- -- ! !
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of October, 1995. Specifications and information herein are subject to change without notice. PS No. 5223-34/34

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